Big structures - Greenarrays GA144 simulator

[didi]

I am testing and learning all about the  Greenarrays  GA144 chip ,  a multicore processor with 144 very simple 32 bit processors, optimized for FORTH, Chuck Moores design - really minimalistic.  



I first have made a disassembler, about one page of code, which is  quite good : http://www.forthseen.de">//http://www.ForthSeen.de, see the section NewLisp.  ( The experts are usually able to shrink my code another 30%  .. ) .



Now I'm trying to write a Simulator for the GA144. For one processor it works quite good, now I'm thinking how to make  144 of them in parallel, and what might be the best  data structures in newLISP.  



This is the structure of one  processor:

Code Select Expand

; g8.lsp 19.October.2014 19:00

; test settings
( set 'DS '( 1 2 3 4 5 6 7 8 ))   ; data stack
( set 'RS '( 11 12 13 14 15 16 17 18 )) ; return stack
( set 'S 9 'T 10 'R 19 'P 0 'A 0 'B 0 'ALU 0 'EXT 0 'CY 0  )  ; registers
( set 'RAM ( array 64 '( 0 ) ))  ; RAM 64 words  each 18 bits
( set 'ROM ( array 64 '( 0 ) ))  ; ROM 64 words dto.
( set 'IO  '( (0x15D "io" 0x15555 )  ; IO-section
  (0x141 "data" 0 ) (0x145 "---u" 0 ) (0x175 "--l-" 0 ) (0x165 "--lu" 0 )
  (0x115 "-d--" 0 ) (0x105 "-d-u" 0 ) (0x135 "-dl-" 0 ) (0x125 "-dlu" 0 )
  (0x1D5 "r---" 0 ) (0x1C5 "r--u" 0 ) (0x1F5 "r-l-" 0 ) (0x1E5 "r-lu" 0 )
  (0x195 "rd--" 0 ) (0x185 "rd-u" 0 ) (0x1B5 "rdl-" 0 ) (0x1A5 "rdlu" 0 ) ))
The GA144  and FORTH are  working mainly on a data-stack, a lot of pushing and poping which is easy in newLISP. But what about 144 such parts

 - different context's ?

 - a big Array ?

 - big lists of list ..

[TedWalther]

Need more info.  How do these 144 cpus interconnect?  Glad you are working with Chuck Moore's chip.  It is the only one I would trust.  I believe all other silicon out there has backdoors inserted by the Verilog compilers, in the same way as described by Ken Thompson in "trusting trust".  http://cm.bell-labs.com/who/ken/trust.html">http://cm.bell-labs.com/who/ken/trust.html

[TedWalther]

Also, what makes each cpu distinct?  Is it the latch address on the mesh bus?  Does it have a serial number or identifier built in?



Personally I'd have an Array, with one entry per cpu, that stores all cpu state.  So, 144 entries.  Then just iterate over the list for each clock tick.

[didi]

The nodes  talk via  the  I/O  ports to each other,  by Default a middle node listens to his 4 neighbours,  if  one of the 4 writes something it starts working.



Let's take the datastack and the push and pop command - that'll be the most used .  Top of stack is  "T"  , second is "S" and than the inner 8 words   DS 1 ... 8.

Everything works as you expect, but  DS is a ring buffer,  If you push in more than 8 words , the first will get lost, thats clear, but if you pop out somethingout, the last entry gets the popped value, too.



This is my first solution:

Code Select Expand

( define ( DSpush x )
  ( push S DS -1 )
  ( pop DS )
  ( set 'S T 'T x ))  

( define ( DSpop )
  ( set 'x T 'T S )
  ( set 'S ( pop DS -1 ) )
  ( push S DS )
  x )

I'll think about an  Array solution, too.  I'll get a lot of indizes.



What about an object oriented solution ?

[TedWalther]

Each "cpu" can be an object.  Having an Array filled with cpu makes it easy to use the array index number to initialize each cpu so it knows which are its neighbors.  You could also make an object for each external pin.  Integer indexes are just easy.

[TedWalther]

Is it true each cpu only has 64 words of memory?  And each word is 18 bit?  So, 36 normal 32 bit words?  However each 18 bit "word" can hold 3 instructions?  So the entire memory space will hold 192 opcodes?  Does the manual describe an addon module for interfacing to ram storage?



This bends my brain; I'd have to spend time, as you are doing, just spending a year or so absorbing the chip one day at a time.  And thank you for doing so; hope you will share your insights.  Does one chip "launch" code to all the others like unreeling a fishing line?  How many opcodes does it take for the farthest chip to send a message to an external pin?  Can intermediary chips block such access requests?



Glad Chuck Moore is still alive.  The passing of Jeff Fox was very sad.  I hope http://ultratechnology.com/">http://ultratechnology.com/ stays up forever.

[didi]

You have  3 and a half slots per word.  So up to 4 commands per word .  There is also a  micronext command, with it you can make a loop within one word  and  other nice Features.. with some outer nodes you can make simple Interfaces to different memories,  I currently use the serial Interface,  one word are 3 bytes .... Here is the  most important document about it - 10 pages - everything you need is in it, quite dense :

http://www.greenarraychips.com/home/documents/greg/DB001-110412-F18A.pdf">//http://www.greenarraychips.com/home/documents/greg/DB001-110412-F18A.pdf



You are right,  I'll soak it in ..   you'll see my small steps in my blog  http://www.forthseen.de">//http://www.ForthSeen.de, (  this blog-generator is also written  in newLISP .. )



I know the ultratechnology page, maybe we should download everything  and mirror it.



I think the combination of newLISP and the GA144 is a thrilling mixture,  both are in there way powerful and minimalistic.



 I am trying the  big array idea !